The present invention relates in general to semiconductor device fabrication methods and resulting structures. More specifically, the present invention relates to fabrication methods and resulting structures for a semiconductor device that reduce shallow trench isolation (STI) undercutting, floating gates, and gate voids without degrading epitaxy quality.
In contemporary semiconductor device fabrication processes a large number of semiconductor devices, such as field effect transistors (FETs) and on-chip capacitors, are fabricated on a single wafer. Some non-planar device architectures, such as vertical field effect transistors (VFETs), employ semiconductor fins and side-gates that can be contacted outside the active region, resulting in increased device density and some increased performance over lateral devices. In contemporary VFET devices, in contrast to conventional FETs, the source to drain current flows through a vertical pillar in a direction that is perpendicular with respect to a horizontal major surface of the wafer or substrate. A VFET can achieve a smaller device footprint because its channel length is decoupled from the contacted gate pitch.